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the execution continues with the next instruction. The execution of INTO
results in the following.
1. Flag register values are pushed on to the Stack.
2. CS value of the return address and IP value of the return address
and IP value of the return address are pushed on to the stack.
3. IP is loaded from the contents of word location 4x4 = 00010H.
4. CS is loaded from the contents of next word location.
5. Interrupt flag and Trap flag are reset to 0.
Thus a branch to ISS takes place. During the ISS, interrupts are disabled.
At the end of ISS, there will be an IRET instruction, returning back to the
interrupted program. Instructions in the ISS procedure perform the
desired response to the error condition.
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6.RESET
Processor initialization or start up is accomplished with activation
(HIGH) of the RESET pin which it shows in table (2). The 8086 RESET
is required to be HIGH for greater than 4 CLK cycles. The 8086 will
terminate operations on the high-going edge of RESET and will remain
dormant as long as RESET is HIGH. The low-going transition of RESET
triggers an internal reset sequence for approximately 10 CLK cycles.
After this interval the 8086 operates normally beginning with the
instruction in absolute location FFFF0H.
Table 2:process initialization register content
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